The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
As fabrication technology reaches nano-levels, combination circuit systems are becoming more prone to manufacturing defects and have a high susceptibility to soft errors. Soft errors occur due to the exponential decrease in device feature size. Soft errors, which are caused by radioactive decay and cosmic rays, can flip the output of a gate and cause an error, if propagated to an output of the circuit.
As complimentary metal-oxide semiconductor (CMOS) technology is continuously improving and shrinking to the nanometer scale, several studies have indicated that high-density chips will be increasingly accompanied by manufacturing defects and susceptible to dynamic faults during the chip operation. Nanoscale devices are limited by several characteristics: most dominant of which are the device's higher defect rates and the increased susceptibility to soft errors.
Reliability in systems can be achieved by redundancy. Redundancy can be added at the module-level, gate-level, transistor-level or even at the software level. At the software level certain software transformations are applied to reduce the vulnerability of critical instructions of a program. The design of reliable systems by using redundant unreliable components was initiated by John von Neumann in the 1950s. Since then, a plethora of research has been conducted to rectify soft errors in combinational and sequential circuits by applying hardware redundancy. For instance, the Generalized Modular Redundancy (GMR) scheme takes into account the probability of occurrence of each combination at the output of a circuit. The redundancy is added to only those combinations that have high probability of occurrence, while the remaining combinations are left un-protected to save area.
The work of El-Maleh et. al. “A finite state machine based fault tolerance technique for sequential circuits,” Microelectronics Reliability, vol. 54, no. 3, pp. 654-661, 2014, incorporated herein by reference in its entirety, describes a fault tolerant technique for sequential circuits that enhances the reliability by introducing redundant equivalent states to the states with high probability of occurrence. Further, K. Mohanram and N. Touba describe in their work “Partial error masking to reduce soft error failure rate in logic circuits,” Proceedings at 16th IEEE Symposium on Computer Arithmetic, 2003, that is incorporated herein by reference in its entirety, a partial error masking scheme based on Triple Modular Redundancy (TMR). The scheme targets the nodes with the highest soft error susceptibility. Two reduction heuristics are described to reduce soft error failure rate, namely, cluster sharing reduction and dominant value reduction. Instead of triplicating the whole logic as in Triple Modular Redundancy (TMR), only those nodes with highest soft error susceptibility are triplicated, the rest of the nodes are clustered and are shared among the triplicated logic.
Teifel proposed in his work “Self-Voting Dual-Modular-Redundancy Circuits for Single-Event-Transient Mitigation,” IEEE Transactions on Nuclear Science, vol. 55, 2008, incorporated herein by reference in its entirety, a Double Modular Redundancy (DMR) scheme that utilizes voting and self-voting circuits to mitigate the effects of single event transients (SETs) in digital integrated circuits. In this work, the Bayesian detection technique from the communications theory has been applied to the voter in DIVER, called soft NMR. In most cases, it is able to identify the correct output even when all duplicated modules are in error. However, this approach has at least double the area overhead.
To protect memories and latches from soft-errors, cell hardening techniques have been described. An example of such an approach is a DICE memory cell as described by T. Calin, M. Nicolaidis, and R. Velazco, in their work “Upset hardened memory design for submicron CMOS technology,” Nuclear Science, IEEE Transactions on, vol. 43, no. 6, pp. 2874-2878, December 1996, that is incorporated herein by reference in its entirety. The DICE memory cell uses twice the number of original transistors (i.e., 12 transistors as compared to 6 transistors), and has a design limitation of being able to tolerate soft errors in memory elements only and not in the combinational logic.
Soft error protection of combinational logic can be achieved by adding redundancy at the transistor-level. As described by M. Nicolaidis in “Time redundancy based soft-error tolerance to rescue nanometer technologies,” in VLSI Test Symposium, 1999. Proceedings. 17th IEEE, 1999, pp. 86-94, which is incorporated herein by reference in its entirety, in such a scheme a circuit is duplicated containing all but last stage gate where the last stage gate is implemented as a code word preserving gate. The last stage gate is either a NOT, NAND or NOR gate with each transistor duplicated and connected in series to preserve the fault-free state that the output had before the transient fault occurred. Recently, the work by El-Maleh et. al. “Defect-tolerant n2-transistor structure for reliable nano-electronic designs,” Computers Digital Techniques, IET, vol. 3, no. 6, pp. 570-580, November 2009, incorporated herein by reference in its entirety, describes a technique to mask defects in combinational circuits by quadrupling every transistor in a circuit, making the area overhead four times the original circuit. A quadded-transistor guarantees the tolerance of all single transistor defects and many multiple defects. In the quadded-transistor structure, each transistor, A, is replaced by a structure that implements the logic function (A+A) (A+A).
The above described protection techniques either describe a gate sizing method that protects only the sensitive gates by symmetrically sizing the NMOS and PMOS transistors, or describe an asymmetric transistor sizing technique (wherein the NMOS and PMOS transistors are sized independently of each other) while assuming that incident particle strikes only the drain of transistors connected to the output of the gate. Accordingly, a fault tolerance technique for combinational circuits is required, which protects the critical gates of the circuit while considering that particles could strike the drain terminal of any transistor of a logic gate. Moreover, in contrast to the above described works, a reliability framework for different protection thresholds, as well as a fault tolerance technique that combats the soft error occurrence problem while accounting for area overhead is required.